1. Quick Start Guide
|Intel® Quartus® Prime Design Suite 21.3|
|IP Version 20.0.1|
The Interlaken (2nd Generation) FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. The design example is also available for Interlaken Look-aside feature.
You can download the compiled hardware design and run it on the Intel® Stratix® 10 GX/TX Transceiver Signal Integrity Development Kit.
The testbench and design example supports numerous variants (parameter combinations) of the Interlaken IP core for H-tile, L-tile and E-tile device variations including NRZ and PAM4 mode. The Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP core generates design examples for all supported combinations of number of lanes and data rates.
Figure 1. Development Steps for the Design Example
The Interlaken (2nd Generation) IP core design example supports the following features:
- Internal TX to RX serial loopback mode
- Automatically generates fixed size packets
- Basic packet checking capabilities
- Ability to use System Console to reset the design for re-testing purpose
- PMA adaptation
Figure 2. High-level Block Diagram for Interlaken (2nd Generation) Design Example
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