1. Quick Start Guide
|Intel® Quartus® Prime Design Suite 21.3
|IP Version 20.0.1
You can download the compiled hardware design and run it on the Intel® Stratix® 10 GX/TX Transceiver Signal Integrity Development Kit.
The testbench and design example supports numerous variants (parameter combinations) of the Interlaken IP core for H-tile, L-tile and E-tile device variations including NRZ and PAM4 mode. The Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP core generates design examples for all supported combinations of number of lanes and data rates.
- Internal TX to RX serial loopback mode
- Automatically generates fixed size packets
- Basic packet checking capabilities
- Ability to use System Console to reset the design for re-testing purpose
- PMA adaptation