1.2. Directory Structure
The Interlaken (2nd Generation) IP core design example file directories contain the following generated files for the design example.
Figure 3. Directory Structure of the Generated Interlaken (2nd Generation) Example Design
The hardware configuration, simulation, and test files are located in
<design_example_installation_dir>/uflex_ilk_0_example_design.
File Names | Description |
---|---|
example_design.qpf | Intel® Quartus® Prime project file. |
example_design.qsf | Intel® Quartus® Prime project settings file |
example_design.sdc jtag_timing_template.sdc |
Synopsys Design Constraint file. You can copy and modify for your own design. |
sysconsole_testbench.tcl | Main file for accessing System Console |
File Name | Description |
---|---|
top_tb.sv | Top-level testbench file. |
File Name | Description |
---|---|
vcstest.sh | The VCS* script to run the testbench. |
vlog_pro.do | The ModelSim* SE or QuestaSim* script to run the testbench. |
xcelium.sh | The Xcelium* script to run the testbench. |
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