Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683672
Date 8/03/2022
Public

1.3. Hardware Design Example Components

The hardware example design connects system and PLL reference clocks and required design components. After you program the device on the Intel® Stratix® 10 GX/TX Transceiver Signal Integrity Development Kit, the example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver.

After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.

The hardware example design includes external PLLs. You can examine the clear text files to view sample code that implements one possible method to connect external PLLs to the Interlaken (2nd Generation) FPGA IP.

Figure 4.  Interlaken (2nd Generation) IP Hardware Design Example High Level Block Diagram for L-tile and H-tile 6.25, 10.3125, 12.5 Gbps Variations
Figure 5.  Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for L-tile and H-tile 25.3 and 25.8 Gbps Variations
The Interlaken (2nd Generation) hardware design example includes the following components:
  1. Interlaken (2nd Generation) FPGA IP
  2. Packet Generator and Packet Checker
  3. JTAG controller that communicates with System Console. You communicate with the client logic through the System Console.
  4. ATX PLL to generate the high-speed serial clock to drive the device transceiver channel for IP core variations that target an Intel® Stratix® 10 L-tile and H-tile device.
    • For 25.3 and 25.8 Gbps data rate variations, one ATX PLL drives two transceiver channels.
    • The frequency value of the tx_serial_clk coming out of the ATX PLL is half of the data rate. For example, the value of tx_serial_clk for 6.25 Gbps data rate variant is 3.125 GHz.
    • The IP core connects the ATX PLL to the tx_pll_locked and tx_pll_powerdown ports. This simple connection model is only one of many options available to you for configuring and connecting the external PLLs in your Interlaken design.

    Refer to Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide for more information on how to use ATX PLL for more than two channels.

Note: The Interlaken (2nd Generation) hardware design example that targets an E-tile device do not require an ATX PLL.
Figure 6.  Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations

The Interlaken (2nd Generation) hardware design example that targets an E-tile PAM4 mode variations requires an additional clock mac_clkin generated by IO PLL. This PLL must use the same reference clock that drives the pll_ref_clk.

Figure 7.  Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations

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