Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683672
Date 8/03/2022
Public

1.4. Generating the Design

Figure 8. Procedure
Follow these steps to generate the hardware example design and testbench:
  1. In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or click File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Stratix 10 (GX/SX/MX/TX) and select device for your design.
  3. In the IP Catalog, locate and double-click Interlaken (2nd Generation) Intel FPGA IP. The New IP Variant window appears.
  4. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click OK. The parameter editor appears.
    Figure 9. Example Design Tab in the Interlaken (2nd Generation) Intel® FPGA IP Parameter Editor
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the PMA Adaptation tab, specify the PMA adaptation parameters if you plan to use PMA adaptation for your E-tile device variations. This step is optional:
    • Select Enable adaptation load soft IP option.
      Note: You must enable Enable Native PHY Debug Master Endpoint (NPDME) option on the IP tab when PMA adaptation is enabled.
    • Select a PMA adaptation preset for PMA adaptation Select parameter.
    • Click PMA Adaptation Preload to load the initial and continuous adaptation parameters.
    • Specify the number of PMA configurations to support when multiple PMA configurations are enabled using Number of PMA configuration parameter.
    • Select which PMA configuration to load or store using Select a PMA configuration to load or store.
    • Click Load adaptation from selected PMA configuration to load the selected PMA configuration settings.
    For more information about the PMA adaptation parameters, refer to the E-tile Transceiver PHY User Guide.
  8. On the Example Design tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware example design.
    Note:

    You must select at least one of the Simulation or Synthesis options generate the Example Design Files.

  9. For Generated HDL Format, only Verilog is available.
  10. For Target Development Kit select the appropriate option.
    Note: The Intel® Stratix® 10 GX/TX Transceiver Signal Integrity Development Kit is only available when your project specifies Intel® Stratix® 10 device part number starting with:
    • 1SG165H/1SG210H/1SG250H/1SG280H/1SX165H/1SX210H/1SX250H/1SX280H/1ST280E/1ST250E (For H-tile)
    • ST280E/1ST250E (For E-tile)
    When you select the Development Kit option, the pin assignments are set according to the Intel® Stratix® 10 Development Kit device part number and may differ from your selected device. If you intend to test the design on hardware on a different PCB, select No development kit option and make the appropriate pin assignments in the .qsf file.
  11. Click Generate Example Design. The Select Example Design Directory window appears.
  12. If you want to modify the design example directory path or name from the defaults displayed (uflex_ilk_0_example_design), browse to the new path and type the new design example directory name.
  13. Click OK.

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