1. Interlaken (2nd Generation) Intel FPGA IP FPGA IP Release Notes
If a release note is not available for a specific IP core version, the
IP core has no changes in that version.
information on IP update releases up to v18.1, refer to the Intel Quartus Prime Design Suite Update Release Notes.
Intel® FPGA IP versions match the
Quartus® Prime Design Suite software versions until v19.1. Starting in
Quartus® Prime Design Suite software version 19.2,
Intel® FPGA IP has a new versioning scheme.
Intel® FPGA IP version (X.Y.Z) number
can change with each
Quartus® Prime software version. A change in:
X indicates a major revision of the IP. If you update the
Quartus® Prime software, you must
regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP
to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP
to include these changes.
1.1. Interlaken (2nd Generation) Intel FPGA IP v20.0.0
Table 1. v20.0.0
support for 25.78125 Gbps data rate.
the data rates support from 25.3 Gbps to 25.28 Gbps and 25.8
Gbps to 25.78125 Gbps.
1.2. Interlaken (2nd Generation) Intel FPGA IP v19.3.0
Table 2. v19.3.0 2020.06.22
The IP now supports Interlaken Look-aside
Added new Enable
Interlaken Look-aside mode parameter in the IP
configure the IP in Interlaken Look-aside mode.
selection parameter is removed from the current
version of the
Added 12.5 Gbps data rate support for number
of lanes 10 in H-tile and E-tile (NRZ mode) IP core
Removed the following signals from the IP:
Added following new signals:
Removed following two offsets from register
Hardware testing of the design example is now
You can test
the design example on
F-series Transceiver-SoC Development Kit.
You can change the data rate and transceiver
reference clock frequency to slightly different values for your
Interlaken (2nd Generation) IP instance that targets
Stratix® 10 H-tile or E-tile device. Refer to this KDB for information
on how to change the data rate.
customize the data rates depending on the tiles.
1.3. Interlaken (2nd Generation) Intel FPGA IP v19.2.1
Table 3. v19.2.1
Quartus® Prime Version
Intel Agilex devices with E-tile
Renamed the Interlaken (2nd Generation) Intel Stratix 10 FPGA
IP to Interlaken (2nd Generation)
Intel® FPGA IP
1.9. Interlaken (2nd Generation) Intel FPGA IP User Guide Archives
IP versions are the same as the
Quartus® Prime Design Suite software versions up to v19.1. From
Quartus® Prime Design Suite software version 19.2 or later, IP cores
have a new IP versioning scheme.
If an IP core version is not listed, the user guide for
the previous IP core version applies.