5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resources
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
3.2. Generating a 5G LPDC-V IP x
3.2.1. 5G LDPC-V IP Parameters
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals Code Rate Index Selection
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

4.2.1. 5G LDPC-V Receiver Signals

All signals are synchronous to clk.
Figure 12. Receiver Top-level Block DiagramThis figure does not show the Avalon streaming interface signals
Table 11.  Receiver Top-level Signals
Name Direction Description
clk Input Clock. All signals are synchronous to clk.
rstn Input Reset, active-low. Assert for at least for 10 clock cycles. Do not send data or parameters when reset is asserted
i_ldpc_paras Input

Align with i_sink_cb_sop.

[0] is base graph (BG) (1 bit):

  • 0:BG1
  • 1:BG2

[6:1] is Zc_idx (6 bits), the index of lifting factor Zc. Choose Zc from Table 5.3.2-1 of TS38.212. Look up the index of Zc in the Lifting Factor table..

[7] is use_crc (1 bit)

  • 0: not use code block CRC
  • 1: use code block CRC (CRC24B)

[17:8] is the number of null bits (10 bits). Plug in the value of K-K’, where K=22Zc(BG1) or 10Zc(BG2). Check the definition of K and K’ in section 5.2.2 in TS 38.212

[20:18] is the code rate index (3 bits). Refer to Code Rate Index Selection. The Code Rate Index table shows the code rate choices supported by the LDPC encoder and decoder IP. The code rate is not the target code rate.

[23:21] is Qm_idx (3 bits):

  • 0:BPSK
  • 1:QPSK
  • 2:16QAM
  • 3: 64QAM
  • 4:256QAM

[44:24] is E (21 bits), the output length of the rate matcher, or equivalently, input length of the de-rate matcher

[59:45] is k0 position (15 bits).Calculate k0 based on Table 5.4.2.1-2 of TS 38.212

[65:60] is max_iter (6 bits), the maximum number of iterations of LDPC decoding.

[66] is use_harq (1 bit)

  • 0: not use HARQ
  • 1: use HARQ

[81:67] is cb_old_len (15 bit), the length of the previously combined code block already stored in DRR. cb_old_len should be less than or equal to codeword_length 1 of the current frame and the max codeword_length of all the previous frames (first frame is when use_harq = 0).

[109:82] is cb_ddr_wraddr (28 bit), the base address to DDR for writing the combined updated code block

[137:110] is cb_ddr_rdaddr (28 bit) base address to DDR for reading the previous combined code block.

[138] is et_dis (1 bit), the decoder early termination disable.

  • 0: enable early termination
  • 1: disable early termination

[139] is red_synd (1 bit), the decoder reduce syndrome checks

  • 0: full syndrome check
  • 1: reduced syndrome check

[154:140] is the limited circular buffer size.
i_sink_data Input

16 LLRs x LLR_W bits per LLR where LLR_W = 6, and 2 of them are fractional bits.

[LLR_W-1:0]: LLR seq# 0, [LLR_W*2-1:LLR_W]: LLR seq #1,...
i_sink_valid Input

Qualifies the i_sink_data signal

When i_sink_valid is not asserted, the IP stops processing input until i_sink_valid signal is reasserted. Asserted when o_sink_ready is asserted.

i_sink_cb_sop Input

Indicates the start of an incoming packet

You cannot have two valid SOPs in any four consecutive clock cycles
i_sink_cb_eop Input Indicates the end of an incoming packet
o_sink_ready Output

Indicates that the receiver is ready to receive data in the next clock cycle. Ignore when rstn is asserted.

The IP can backpressure incoming data by deasserting this signal: when you see o_sink_ready==0, deassert i_sink_valid in the next clock cycle

o_source_data Output

LDPC decoded hard bits, including code block CRC bit, not including NULL padding (K-K').

data[0] -> bit0, data[1] -> bit1,…,data[31] -> bit31
o_source_valid Output The receiver asserts this signal when o_source_data holds valid data
o_source_cb_sop Output The receiver asserts this signal to indicate the start of a packet
o_source_cb_eop Output The receiver asserts this signal to indicate the end of a packet
o_ldpc_metrics Output
[0] is source_crc_pass (1 bit)
  • 1:pass
  • 0:fail or not checked, align with EOP

[1] is source_et_pass (1 bit): refer to 5G LDPC Intel FPGA IP User Guide, align with SOP

[7:2] is source_iter (6 bits): refer to 5G LDPC Intel FPGA IP User Guide, align with SOP.

avmm_address Output DDR SDRAM 28 bits address (Avalon memory-mapped master)
avmm_read Output DDR read request (Avalon memory-mapped master)
avmm_readdata Input DDR read data with 128*LLR_W bit width (Avalon memory-mapped master)
avmm_readdatavalid Input DDR read data valid (Avalon memory-mapped master)
avmm_write Output DDR write request (Avalon memory-mapped master)
avmm_writedata Output DDR write data with 128*LLR_W bit width (Avalon memory-mapped master)
avmm_waitrequest Input DDR wait request (Avalon memory-mapped master)

Code Rate Index Selection

Let:
  • BG = base graph index i_ldpc_paras[0]
  • CR = code rate index i_ldpc_paras(20:18)
  • num_null = number of null bits i_ldpc_paras[17:8]
  • nb = { {NaN, 66, 55, 44, 33, 30, 27, 25}, { 50, 30, 25, 20, 15,NaN,NaN,NaN} }; 


Step 1.
K = (BG == 0 ? 22 : 10) * Zc;
if (K0 < K - 2*Zc - num_null) // K0 is before NULLs
L = K0 + E + num_null;
else // K0 is after NULLs, since K0 cannot be inside of NULLs
L = K0 + E;

Step 2.
LCB = max(min(Ncb, L), cb_old_len); // if HARQ is not enabled, then LCB = min(Ncb, L);

Step 3.
if (BG == 0) { // BG#1
for (CR = 7; CR >= 1 && LCB > nb[BG][CR]*Zc; CR--) {}
else { // BG#2
      for (CR = 4; CR >= 0 && LCB > nb[BG][CR]*Zc; CR--) {} 
} // choose largest CR s.t. LCB <= nb[BG][CR]*Zc
Related Information
1 codeword_length = nb[BG][CR] * Zc
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