5G LDPC-V Intel® FPGA IP User Guide

ID 683670
Date 12/12/2022

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Document Table of Contents

4.1.1. 5G LDPC-V Transmitter Signals

All signals are synchronous to clk.
Figure 11. Transmitter SignalsThis figure does not show the Avalon streaming interface signals
Table 8.  Transmitter Top-Level Signals
Name Direction Description
clk Input Clock. All signals are synchronous to clk.
rstn Input Reset, active-low. Assert for at least for 10 clock cycles.



Aligns with i_sink_cb_sop

[0] is base graph (BG) (1 bit), where: 0:BG1, 1:BG2

[6:1] is Zc_idx (6 bits)

BG is the index of the lifting factor Zc. Choose Zc from Table 5.3.2-1 of TS 38.212. Look up the index of Zc in Lifting Factor Index table.

[7] is use_crc (1 bit), where 0: not use code block CRC; 1: use code block CRC (CRC24B).

[17:8] is the number of null bits (10 bits). Plug in the value of K-K’, where K=22Zc(BG1) or 10Zc(BG2). Check the definition of K and K’ in 5.2.2 in TS 38.212.

[20:18] is the code rate index (3 bits). The Code Rate table shows the code rate choices supported by the LDPC encoder and decoder IP. The code rate is not target code rate.

[23:21] is Qm_idx (3 bits):

  • 0:BPSK
  • 1:QPSK
  • 2:16QAM
  • 3: 64QAM
  • 4:256QAM

[44:24] is E (21 bits), output length of the rate matcher, or equivalently, input length of the derate matcher.

[59:45] is k0 position (15 bits). Calculate k0 based on Table of TS 38.212.

[74:60] is limited circular buffer size.

i_sink_data Input

32 message bits.

  • [0]: msg seq# 0
  • [1]: msg seq# 1
  • [31]: msg seq# 31

Total number of input bits is K’ if CRC is not used; K’-24 if CRC is used

i_sink_valid Input

Qualifies the i_sink_data signal

When i_sink_valid is not asserted, the IP stops processing input until i_sink_valid signal is reasserted. Assert when o_sink_ready is asserted.

i_sink_cb_sop Input

Indicates the start of an incoming packet

You cannot have two valid SOPs in any five consecutive clock cycles

i_sink_cb_eop Input Indicates the end of an incoming packet
i_source_ready Input Assert this signal to inform the transmitter that the downstream is ready to take transmitter outputs. The downstream should have readyAllowance of up to 30 clock cycles. The transmitter can produce up to 30 cycles of valid data after i_source_ready is deasserted.
o_sink_ready Output

Indicates that the receiver is ready to receive data in the next clock cycle. Ignore when rst is asserted.

The IP can backpressure incoming data by deasserting this signal. When o_sink_ready==0 is observed, deassert i_sink_valid in the next clock cycle.

o_source_data Output

32 output bits from rate matcher

  • data[0] -> bit0
  • data[1] -> bit1
  • data[31] -> bit31

Total number of output bits is E.

o_source_valid Output The transmitter asserts this signal when o_source_data holds valid data.
o_source_cb_sop Output The transmitter asserts this signal to mark the start of a packet.
o_source_cb_eop Output The transmitter asserts this signal to mark the end of a packet