5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resources
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
3.2. Generating a 5G LPDC-V IP x
3.2.1. 5G LDPC-V IP Parameters
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

3.2.1. 5G LDPC-V IP Parameters

Table 7.  5G LDPC-V Parameters
Parameter Name Blocks Description
Configuration.
Dual Decoder, LDPC2 Zmax = 192
  • LDPC1
  • LDPC2
  • Derate matching
  • HARQ
  • CRC
 LDPC1 is a standard LDPC engine that processes all codewords. LDPC2 can increase throughput by processing smaller codewords up to Zmax= 192.
Dual Decoder, LDPC2 Zmax = 192 with DSPs Same as Dual Decoder, LDPC2 Zmax = 192 but with DSPs to reduce ALM usage.
Single Decoder, Standard
  • LPDC
  • Derate matching
  • HARQ
  • CRC
 Standard design.
Single Decoder, Standard using DSP Same as Single Decoder, Standard using DSP but with DSPs to reduce ALM usage.
Single Decoder, Lite This design achieve lower power.
Single Decoder, Super-Lite This design is configured to achieve lowest power.
Figure 6. 5G LDPC Parameter Editor
Level Two Title