3.1.1. TX MAC Adapter
The TX MAC adapter controls the data transmission to the user logic using the Avalon® streaming interface. This block supports user-defined information transmission and flow control.
Transferring User-defined Information
In Full mode, the IP provides the tx_is_usr_cmd signal that you can use to initiate user-defined information cycle such as XOFF/XON transmission to the user logic. You can initiate the user-defined information transmission cycle by asserting this signal and transfer the information using tx_avs_data along with the assertion of tx_avs_startofpacket and tx_avs_valid signals. The block then deasserts the tx_avs_ready for two cycles.
- When tx_avs_startofpacket is asserted, tx_avs_ready is deasserted for one clock cycle.
- When tx_avs_endofpacket is asserted, tx_avs_ready is deasserted for one clock cycle.
- When any paired CWs is asserted tx_avs_ready is deasserted for two clock cycles.
- When RS-FEC alignment marker insertion occurs at the custom PCS interface, tx_avs_ready is deasserted for four clock cycles.
- Every 17 Ethernet core clock cycles in PAM4 modulation mode and every 33 Ethernet core clock cycles in NRZ modulation mode. The tx_avs_ready is deasserted for one clock cycle.
- When user logic deasserts tx_avs_valid during no data transmission.