Serial Lite IV Intel® FPGA IP User Guide

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ID 683655
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® FPGA IP User Guide 2. Serial Lite IV Intel® FPGA IP Overview 3. Functional Description 4. Getting Started 5. Parameters 6. Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with Serial Lite IV Intel® FPGA IP 8. Serial Lite IV Intel® FPGA IP Registers 9. Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Functional Description x
3.1. TX Datapath 3.2. RX Datapath 3.3. Serial Lite IV Intel® FPGA IP Clock Architecture 3.4. Reset and Link Initialization 3.5. Link Rate and Bandwidth Efficiency Calculation
3.1. TX Datapath x
3.1.1. TX MAC Adapter 3.1.2. Control Word (CW) Insertion 3.1.3. TX CRC 3.1.4. TX MII Encoder 3.1.5. TX PCS and PMA
3.1.2. Control Word (CW) Insertion x
3.1.2.1. Start-of-burst CW 3.1.2.2. End-of-burst CW 3.1.2.3. Alignment Paired CW 3.1.2.4. Empty-cycle CW 3.1.2.5. Idle CW 3.1.2.6. Data Word
3.2. RX Datapath x
3.2.1. RX PCS and PMA 3.2.2. RX MII Decoder 3.2.3. RX CRC 3.2.4. RX Deskew 3.2.5. RX CW Removal
3.4. Reset and Link Initialization x
3.4.1. TX Reset and Initialization Sequence 3.4.2. RX Reset and Initialization Sequence 3.4.3. PMA Adaptation Flow
3.4.3. PMA Adaptation Flow x
3.4.3.1. Starting the PMA Adaptation Flow
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Parameters and Options 4.3. Generated File Structure 4.4. Simulating Intel® FPGA IP Cores 4.5. Synthesizing IP Cores in Other EDA Tools 4.6. Compiling the Full Design
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.4. Simulating Intel® FPGA IP Cores x
4.4.1. Simulating and Verifying the Design
6. Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines 7.3. E-Tile Channel Placement Tool
1. About the Serial Lite IV Intel® FPGA IP User Guide
2. Serial Lite IV Intel® FPGA IP Overview
3. Functional Description
4. Getting Started
5. Parameters
6. Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with Serial Lite IV Intel® FPGA IP
8. Serial Lite IV Intel® FPGA IP Registers
9. Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

10. Document Revision History for the Serial Lite IV Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 5.1.0
  • Updated product family name to " Intel Agilex® 7".
  • Updated Table: Serial Lite IV Intel FPGA IP Release Information.
  • Updated Table: IP Version and Support Level.
2023.02.10 22.4 4.0.0
  • Added topic: Starting the PMA Adaptation Flow.
  • Updated Table: Reset Signals
  • Updated Table: Serial Lite IV Intel FPGA IP Release Information
  • Updated Table: IP Version and Support Level
2022.11.11 21.3 1.3.1
  • Updated Figure: RX Reset and Initialization Timing Diagram
  • Updated Serial Lite IV Intel® FPGA IP User Guide Archives
2021.12.01 21.3 1.3.1
  • Added new Table: Signal Mapping Between Serial Lite IV Intel® FPGA IP and E-Tile Hard IP for Ethernet Intel® FPGA IP .
  • Corrected the Transceiver data rate values for NRZ with RS-FEC enabled mode in Table: IP from "10.3125 Gbps to 28.0 Gbps" to "10.000 Gbps to 28.0 Gbps".
2021.11.01 21.3 1.3.1 Added support for QuestaSim* simulator.
2021.10.04 21.2 1.3.1
  • Updated the guideline for error condition during deskew process in Table: Error Condition and Handling Guidelines.
2021.08.18 21.2 1.3.1
  • Updated the following topics:
    • TX Reset and Initialization Sequence
    • RX Reset and Initialization Sequence
  • Updated the following Figures: RX Reset and Initialization Timing Diagram and TX Reset and Initialization Timing Diagram.
  • Corrected the description for reconfig_reset to clarify that this signal is an active-high reset signal in Table: Reset Signals.
  • Removed support for NCSim in the following tables:
    • Table: Serial Lite IV IP Core Generated Files
    • Table: Intel FPGA IP Core Simulation Scripts
2021.04.09 21.1 1.3.1
  • Updated RX Reset and Initialization Sequence.
  • Made minor editorial edits to the document.
2021.04.01 21.1 1.3.1
  • Added new parameters to Table: IP:
    • Preserve unused transceiver channels for PAM4
    • Reference clock frequency for preserved channels
  • Updated the Transceiver data rate value for PAM4 mode in Table: IP from 32.0 Gbps to 32.5 Gbps.
  • Added a new interface signal—xcvr_ref_clk_1.
  • Updated the following tables:
    • Serial Lite IV Intel® FPGA IP Release Information
    • IP Version and Support Level
2020.03.12 19.4 1.2.0
  • Updated effective rates for PAM4 transceiver mode in the Bandwidth Efficiency table.
  • Removed the effective rate calculation for PAM4 in the Link Rate and Bandwidth Efficiency Calculation topic.
  • Added PMA Adaptation Flow topic and link to the Ethernet Adaptation Flow with Non-external AIB Clocking in the E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs user guide.
2020.01.23 19.4 1.2.0
  • Added ALM count and IP latency for NRZ with RS-FEC enabled mode in the Intel® Stratix® 10 Serial Lite IV Intel FPGA IP Resource Utilization and Intel Agilex® 7 Serial Lite IV Intel FPGA IP Resource Utilization tables.
  • Added bandwidth efficiency values for NRZ with RS-FEC enabled mode in the Bandwidth Efficiency table.
  • Updated the effective rate calculations for both NRZ and PAM4 features in the Link Rate and Bandwidth Efficiency Calculation topic.
  • Updated values for the following parameters in the Parameters topic:
    • Transceiver data rate
    • Set user-defined IP identifier
  • Updated rsfec_reconfig_address signals description for NRZ mode.
  • Added description to decode addresses and lane numbers for the phy_reconfig_address and xcvr_reconfig_address signals.
2019.09.30 19.3 1.1.0
  • Changed IP name to Serial Lite IV Intel FPGA IP.
  • Added support for Intel Agilex® 7 devices.
  • Added support for NRZ mode.
  • Added information for CRC feature.
  • Updated PCS, PMA and RS-FEC reconfiguration signals width.
2019.07.01 19.2 1.0.0 Initial release.
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