Creating Heterogeneous Memory Systems in Intel® FPGA SDK for OpenCL Custom Platforms

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ID 683654
Date 12/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms
1. Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms x
1.1. Verifying the Functionality of the FPGA Board and the EMIF Interfaces 1.2. Modifying the board_spec.xml File 1.3. Setting Up Multiple Memory Dividers in Qsys 1.4. Modifying the Boardtest Program and the Host Code for Your Heterogeneous Memory Solution 1.5. Verifying the Functionality of Your Heterogeneous Memory System 1.6. Document Revision History
1. Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms

1.5. Verifying the Functionality of Your Heterogeneous Memory System

To ensure that the heterogeneous memory system functions properly, unset the CL_CONTEXT_COMPILER_MODE_INTELFPGA flag in your host code.

In OpenCL™ systems with homogeneous memory, you have to option to set the CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 flag in your host code to disable the reading of the .aocx file and the reprogramming of the FPGA. Setting the CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 flag is useful when instantiating your board to verify the functionality of your Custom Platform without designing the floorplan and specifying the LogicLock™ regions.

With heterogeneous memory systems, the runtime environment must read the buffer locations of each buffer, described in the .aocx file, to verify the memory systems' functionality. However, you might want to verify the functionality of your Custom Platform without implementing the final features of the board design, such as designing the floorplan and specifying the LogicLock™ regions.

  1. Verify that the CL_CONTEXT_COMPILER_MODE_INTELFPGA flag is unset in your host code.
  2. Browse to the board/<board name>/source/host/mmd directory of your Custom Platform.
  3. Open the acl_pcie_device.cpp memory-mapped device (MMD) file in a text editor.
  4. Modify the reprogram function in the acl_pcie_device.cpp file by adding a return 0; line, as shown below: 
    int ACL_PCIE_DEVICE::reprogram(void *data, size_t data_size)
{
   return 0;

   // assume failure
   int reprogram_failed = 1; 

   // assume no rbf or hash in fpga.bin
   int rbf_or_hash_not_provided = 1; 

   // assume base and import revision hashes do not match
   int hash_mismatch = 1; 
   ...
}
  5. Recompile the acl_pcie_device.cpp file.
  6. Verify that the CL_CONTEXT_COMPILER_MODE_INTELFPGA flag remains unset.
Attention: After you add return 0; to the reprogram function and recompile the MMD file, the runtime environment will read the .aocx file and assign the buffer locations but will not reprogram the FPGA. You must manually match the FPGA image with the .aocx file. To reverse this behavior, remove return 0; from the reprogram function and recompile the MMD file.
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