Creating Heterogeneous Memory Systems in Intel® FPGA SDK for OpenCL Custom Platforms

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ID 683654
Date 12/13/2016
Public
Document Table of Contents
Document Table of Contents x
1. Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms
1. Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms x
1.1. Verifying the Functionality of the FPGA Board and the EMIF Interfaces 1.2. Modifying the board_spec.xml File 1.3. Setting Up Multiple Memory Dividers in Qsys 1.4. Modifying the Boardtest Program and the Host Code for Your Heterogeneous Memory Solution 1.5. Verifying the Functionality of Your Heterogeneous Memory System 1.6. Document Revision History
1. Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms

1.2. Modifying the board_spec.xml File

Modify the board_spec.xml file to specify the types of heterogeneous memory systems that are available to the OpenCL kernels.
During kernel compilation, the Intel® FPGA SDK for OpenCL™ Offline Compiler assigns kernel arguments to a memory based on the buffer location argument that you specify.
  1. Browse to the board_spec.xml file in the hardware directory of your Custom Platform.
  2. Open the board_spec.xml file in a text editor and modify the XML accordingly.
    For example, if your hardware system has two DDR memories as default global memory and two QDR banks that you model as heterogeneous memory, modify the memory sections of the board_spec.xml file to resemble the following: 
    <!-- DDR3-1600 -->
<global_mem name="DDR" max_bandwidth="25600" interleaved_bytes="1024"
            config_addr="0x018">
  <interface name="board" port="kernel_mem0" type="slave" width="512"
             maxburst="16" address="0x00000000" size="0x100000000"
             latency="240"/>
  <interface name="board" port="kernel_mem1" type="slave" width="512"
             maxburst="16" address="0x100000000" size="0x100000000"
             latency="240"/>
</global_mem>

<!-- QDRII -->
<global_mem name="QDR" max_bandwidth="17600" interleaved_bytes="8"
            config_addr="0x100">
  <interface name="board" type="slave" width="64" maxburst="1"
             address="0x200000000" size="0x1000000" latency="1
             addpipe="1">
    <port name="kernel_qdr0_r" direction="r"/>
    <port name="kernel_qdr0_w" direction="w"/>
  </interface>
  <interface name="board" type="slave" width="64" maxburst="1"
             address="0x201000000" size="0x1000000" latency="150"
             addpipe="1">
    <port name="kernel_qdr1_r" direction="r"/>
    <port name="kernel_qdr1_w" direction="w"/>
  </interface>
</global_mem>
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