1.3. Setting Up Multiple Memory Dividers in Qsys
Currently, the OpenCL™ Memory Bank Divider in the the Qsys design does not support non-power-of-2 number of memory banks, which is not a limitation for typical configurations. However, there are scenarios where non-power-of-2 number of memory interfaces are necessary.
To accommodate non-power-of-2 number of memory interfaces, use multiple OpenCL Memory Bank Dividers to create heterogeneous memory systems with non-power-of-2 number of memory banks.
You must create multiple OpenCL Memory Bank Dividers when you have a true heterogeneous memory system. Consider a system with one DDR memory interface and one QDR memory interface. Because the two banks have different memory topologies, you cannot combine them under a single global memory.
Figure 1. Block Diagram of a Three-Bank Heterogeneous Memory SystemThis heterogeneous memory system contains two DDR memory interfaces and one QDR memory interface.
If you are using version 16.0, 16.0.1, or 16.0.2 of the Intel® Quartus® Prime software and the Altera SDK for OpenCL, the OpenCL Memory Bank Divider incorrectly handles memory bursts across address boundaries. To work around this known issue, add a pipeline bridge with a burst size of 1 and connect its Avalon® Memory-Mapped (Avalon®-MM) master to the OpenCL Memory Bank Divider's slave port.
Note: This known issue is fixed in the Intel® Quartus® Prime software and the Intel® FPGA SDK for OpenCL™ version 16.1.
Figure 2. Block Diagram of a Three-Bank Heterogeneous Memory System with a Pipeline Bridge