AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

ID 683652
Date 9/28/2020

1.6. Test Result Comments

In each test case, the RX JESD204C Intel® FPGA IP successfully establishes the sync header alignment, extended multiblock alignment, and until user data phase.

No data integrity issue is observed by the ramp checker for JESD configurations at different lanes rates covering all physical lanes, also no cyclic redundancy check (CRC) and command parity error is observed.

In the deterministic latency measurement, consistent RBD count and total latency between the AD9081 ADC input and the JESD Intel® FPGA IP transport layer output are observed across multiple power cycles or resets.

To avoid lane de-skew error and achieve deterministic latency, the LEMC or RBD offset need to be programmed in the JESD204C RX IP for a few JESD configurations. The modes as stated in the table below.

Mode (LMF) rbd_offset (sysref_ctrl[24:16]) lemc_offset (sysref_ctrl[15:8])
841 14 Default. Compile-time specific.
882 14 13
6.12.4 14 Default. Compile-time specific.