AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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Date 9/28/2020
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Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer (TL) 1.3.3. Deterministic Latency - Subclass 1 (DL)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Sync Header Alignment (SHA) 1.3.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices

1.5. Test Results

The following table contains the possible results and their definition.

Table 6.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 7.  Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2
Test L M F Data Rate (Gbps) ADC Sampling Clock (MHz) FPGA Link Clock (MHz) 9 FPGA Frame Clock (MHz)9 Result
1 8 4 1 24.75000 3000.00 187.50 375.00 PASS
2 8 16 4 20.46000 2480.00 155.00 155.00 PASS
3 8 8 6 12.16512 2949.12 92.16 368.64 PASS
4 8 2 1 12.16512 2949.12 92.16 368.64 PASS
5 8 8 2 16.22016 2949.12 122.88 122.88 PASS
6 4 4 2 18.48000 3360.00 140.00 140.00 PASS
7 4 8 4 12.16512 2949.12 92.16 92.16 PASS
8 8 2 3 9.12384 2949.12 69.12 276.48 PASS
9 8 8 2 8.11008 2949.12 61.44 61.44 PASS
10 8 2 1 12.67200 3072.00 96.00 384.00 PASS
11 6 12 4 22.77000 2760.00 172.50 172.50 PASS
12 3 6 4 14.85000 2760.00 112.50 112.50 PASS
13 2 8 8 11.88000 2880.00 90.00 90.00 PASS

The following table shows the results for test cases DL.1, DL.2, and DL.3 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8.  Result for Deterministic Latency Test
Test L M F Data Rate (Gbps) ADC Sampling Clock (MHz) FPGA Link Clock (MHz)9 FPGA Frame Clock (MHz)9 Result RBD Count Latency (Frame Clock Cycles) Latency (Equivalent Link Clock Cycles)
DL.1 8 4 1 24.75000 3000.00 187.50 375.00 PASS 14 96 48
DL.2 8 4 1 24.75000 3000.00 187.50 375.00 PASS
DL.3 8 4 1 24.75000 3000.00 187.50 375.00 PASS
DL.1 8 16 4 20.46000 2480.00 155.00 155.00 PASS 5 91 91
DL.2 8 16 4 20.46000 2480.00 155.00 155.00 PASS
DL.3 8 16 4 20.46000 2480.00 155.00 155.00 PASS
DL.1 8 8 6 12.16512 2949.12 92.16 368.64 PASS 28 244 61
DL.2 8 8 6 12.16512 2949.12 92.16 368.64 PASS
DL.3 8 8 6 12.16512 2949.12 92.16 368.64 PASS
DL.1 8 2 1 12.16512 2949.12 92.16 368.64 PASS 5 164 41
DL.2 8 2 1 12.16512 2949.12 92.16 368.64 PASS
DL.3 8 2 1 12.16512 2949.12 92.16 368.64 PASS
DL.1 8 8 2 16.22016 2949.12 122.88 122.88 PASS 14 55 55
DL.2 8 8 2 16.22016 2949.12 122.88 122.88 PASS
DL.3 8 8 2 16.22016 2949.12 122.88 122.88 PASS
DL.1 4 4 2 18.48000 3360.00 140.00 140.00 PASS 2 66 66
DL.2 4 4 2 18.48000 3360.00 140.00 140.00 PASS
DL.3 4 4 2 18.48000 3360.00 140.00 140.00 PASS
DL.1 4 8 4 12.16512 2949.12 92.16 92.16 PASS 5 91 91
DL.2 4 8 4 12.16512 2949.12 92.16 92.16 PASS
DL.3 4 8 4 12.16512 2949.12 92.16 92.16 PASS
DL.1 8 2 3 9.12384 2949.12 69.12 276.48 PASS 20 224 56
DL.2 8 2 3 9.12384 2949.12 69.12 276.48 PASS
DL.3 8 2 3 9.12384 2949.12 69.12 276.48 PASS
DL.1 8 8 2 8.11008 2949.12 61.44 61.44 PASS 10 54 54
DL.2 8 8 2 8.11008 2949.12 61.44 61.44 PASS
DL.3 8 8 2 8.11008 2949.12 61.44 61.44 PASS
DL.1 8 2 1 12.67200 3072.00 96.00 384.00 PASS 5 165 42
DL.2 8 2 1 12.67200 3072.00 96.00 384.00 PASS
DL.3 8 2 1 12.67200 3072.00 96.00 384.00 PASS
DL.1 6 12 4 22.77000 2760.00 172.50 172.50 PASS 14 86 86
DL.2 6 12 4 22.77000 2760.00 172.50 172.50 PASS
DL.3 6 12 4 22.77000 2760.00 172.50 172.50 PASS
DL.1 3 6 4 14.85000 2700.00 112.50 112.50 PASS 7 89 89
DL.2 3 6 4 14.85000 2700.00 112.50 112.50 PASS
DL.3 3 6 4 14.85000 2700.00 112.50 112.50 PASS
DL.1 2 8 8 11.88000 2880.00 90.00 90.00 PASS 9 117 117
DL.2 2 8 8 11.88000 2880.00 90.00 90.00 PASS
DL.3 2 8 8 11.88000 2880.00 90.00 90.00 PASS
9 The frame clock and link clock are derived from the core clock using an internal core PLL.
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