AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683652
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer (TL) 1.3.3. Deterministic Latency - Subclass 1 (DL)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Sync Header Alignment (SHA) 1.3.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices

1.3.1.1. Sync Header Alignment (SHA)

Table 1.  Sync Header Alignment Test Cases
Test Case Objective Description Passing Criteria
SHA.1 Check if Sync Header Lock is asserted after the completion of reset sequence. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_rst_n
  • j204c_rx_sh_lock
  • j204c_rx_int 1

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_sh_lock is asserted after the deassertion of j204c_rx_rst_n.
  • The j204c_rx_int 1 signal should stay low if there is no error.
SHA.2 Check Sync Header Lock status after sync header lock is achieved (or during the Extended Multi-Block Alignment phase) and stable. The following signals in <ip_variant_name> _base.v are tapped
  • j204c_rx_sh_lock
  • j204c_rx_int 1

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_sh_lock is asserted.
  • The j204c_rx_int1 signal is deasserted if there is no error.
1 The error interrupts that are enabled by default is sufficient for passing criteria.
Level Two Title