AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

ID 683652
Date 9/28/2020

1.3.1. Receiver Data Link Layer

This test area covers the test cases for sync header alignment (SHA) and extended multiblock alignment (EMBA).

On link start up, after the receiver reset, the JESD204C Intel® FPGA IP starts looking for the sync header stream that is transmitted by the device. The Signal Tap logic analyzer tool monitors the receiver data link layer operation.