Errata Sheet and Guidelines for MAX 10 ES Devices

Download PDF
ID 683630
Date 6/12/2015
Public
Document Table of Contents
Document Table of Contents x
1. Device Errata for MAX 10 ES Devices 2. Device Guidelines for MAX® 10 ES Devices 3. Document Revision History
1. Device Errata for MAX 10 ES Devices x
1.1. ADC Prescalar 1.2. ESD Performance 1.3. Timing Model Adjustment
2. Device Guidelines for MAX® 10 ES Devices x
2.1. Recommended Power-up Sequencing for MAX 10 ES Devices 2.2. Full Chip Erase Prior to Initial Device Programming 2.3. Migration Guidelines
1. Device Errata for MAX 10 ES Devices
2. Device Guidelines for MAX® 10 ES Devices
3. Document Revision History

1.3. Timing Model Adjustment

To better align the Quartus® II timing models with silicon characterization, Altera recommends adjusting the timing for I/O-to-Core and Core-to-I/O data transfer in MAX® 10 ES devices. For temporary solution, add 300 ps (0.3 ns) clock uncertainty in TimeQuest Timing Analyzer.

To add 300 ps (0.3 ns) clock uncertainty in TimeQuest Timing Analyzer, add the following constraints in the Synopsys Design Constraints File (.sdc):

  • set_clock_uncertainty –setup –to <clock name> -setup –add 0.3
  • set_clock_uncertainty –hold –enable_same_physical_edge –to <clock name> –add 0.3

For example:

set_clock_uncertainty -to { inst|altpll_component|auto_generated|pll1|clk[1] } -setup 0.3

After adding the .sdc file constraint, a clock uncertainty row is added in Data Required Path in the timing report.

Figure 1. Timing Report Before 300 ps Clock Uncertainty is Added
Figure 2. Timing Report After 300 ps Clock Uncertainty is Added
Level Two Title