F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 12/04/2023
Public
Document Table of Contents
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4.5. IP Reset

The Interlaken IP core variations have a single asynchronous reset, the reset_n signal. The Interlaken IP core manages the initialization sequence internally. After you de-assert reset_n (raise it after asserting it low), the IP core automatically goes through the entire reset sequence.

The reset_n signal only reset the IP core, while the tx_rst_n and rx_rst_n signals reset the soft reset controller of the F-tile.

The tx_rst_ack_n and rx_rst_ack_n are active low asynchronous reset acknowledge signals for F-tile which indicate that the soft reset controller has successfully entered reset mode and you can now release the reset_n, tx_rst_n, and rx_rst_n signals. The tx_rst_ack_n and rx_rst_ack_n signals stay low until you release the tx_rst_n, and rx_rst_n signals respectively.
Figure 26. Reset Timing Diagram

Following completion of the reset sequence internally, the Interlaken IP core begins link initialization. If your IP core and its Interlaken link partner initialize the link successfully, you can observe the assertion of the lane and link status signals according to the Interlaken specification. For example, you can monitor the tx_lanes_aligned, sync_locked, word_locked, and rx_lanes_aligned output status signals.

For details on transceiver initialization, please refer to the F-Tile Architecture PHY IP User Guide.