F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 12/04/2023
Public
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2.2. Generated File Structure

The Intel® Quartus® Prime Pro Edition software generates the following output file structure for F-Tile Interlaken Intel® FPGA IP core.
Figure 4. IP Generated Files
Table 10.  IP Generated Files

File Name

Description

<your_ip>.ip

The top-level IP variation file. <your_ip> is the name that you give your IP variation.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.

This IP does not support VHDL. However, the Intel® Quartus® Prime Pro Edition software generates this file.

<your_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<your_ip>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_ip>.qgsimc Lists simulation parameters to support incremental regeneration.
<your_ip>.qgsynthc Lists synthesis parameters to support incremental regeneration.
<your_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Intel® Quartus® Prime software.

<your_ip>.sopcinfo

Describes the connections and IP component parameterizations in your Platform Designer system. You can parse its contents to get requirements when you develop software drivers for IP components.

<your_ip>.csv Contains information about the upgrade status of the IP component.
<your_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_ip>.xml Contains information about interfaces and parameters of the IP component.
<your_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<your_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.

This IP does not support VHDL. However, the Intel® Quartus® Prime Pro Edition software generates the _inst.vhd file.

<your_ip>.v HDL files that instantiates each submodule or child IP for synthesis or simulation.
mentor/

Contains a Siemens* EDA QuestaSim* script msim_setup.tcl to set up and run a simulation.

synopsys/vcs/

Contains a shell script vcs_setup.sh to set up and run a Synopsys* VCS* simulation.

synopsys/vcsmx/

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a Synopsys* VCS* MX simulation.

xcelium/

Contains a shell script xcelium_setup.sh file to set up and run a Cadence* Xcelium* simulation.

<child IP cores>/ For each generated child IP directory, Platform Designer generates synth/ and sim/ sub-directories.