F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 12/04/2023
Public
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6. IP Registers

The Interlaken IP core control registers are 32 bits wide and are accessible to you using the management interface, an Avalon® memory-mapped interface which conforms to the Avalon Interface Specifications.
Note: All unlisted locations are reserved.
The FGT and FHT PMA registers are 32 bits wide and are accessible to you using the Transceiver Reconfiguration Interface, an Avalon® memory-mapped interface which conforms to the Avalon Interface Specifications.
The FEC registers are 32 bits wide and are accessible to you using the Interlaken Reconfiguration Interface, an Avalon® memory-mapped interface which conforms to the Avalon Interface Specifications.