eSRAM Intel® FPGA IP Release Notes

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ID 683604
Date 9/26/2022
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Document Table of Contents x
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes 2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes x
1.1. eSRAM Intel Agilex® 7 FPGA IP v20.1.0 1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0 1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1 1.4. eSRAM Intel Agilex® 7 FPGA IP v19.2.0 1.5. eSRAM Intel Agilex® 7 FPGA IP v19.1.2 1.6. eSRAM Intel Agilex® 7 FPGA IP v19.1.1 1.7. Intel Agilex® 7 Embedded Memory User Guide Archives
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices) x
2.1. eSRAM Intel® FPGA IP v19.2.0 2.2. eSRAM Intel® FPGA IP v19.1.5 2.3. eSRAM Intel® FPGA IP v19.1.4 2.4. eSRAM Intel® FPGA IP v19.1.3 2.5. eSRAM Intel® FPGA IP v18.1 2.6. eSRAM Intel® FPGA IP v18.0 2.7. Native eSRAM IP Core v17.1 2.8. Intel® Stratix® 10 Embedded Memory User Guide Archives
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)

2.3. eSRAM Intel® FPGA IP v19.1.4

Table 9.  v19.1.4 2020.08.03
Intel® Quartus® Prime Version Description Impact
20.2

Renamed the I/O PLL filename to waive the warning message from the IOPLL file.

If the two eSRAMs have the same PLL parameters (PLL reference clock frequency and PLL desired clock frequency), the warning message can be ignored.

If the two eSRAMs have different PLL parameters, after compilation they will be set to the same PLL frequencies taken from one of the eSRAM Intel® FPGA IP parameters. Refer to the Quartus Fitter report > Plan Stage > PLL Usage Summary to observe the implemented eSRAM IOPLL frequencies.

IP update is needed when the PLL parameter for both eSRAM is different.

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