1.1. eSRAM Intel Agilex® 7 FPGA IP v20.1.0
1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0
1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1
1.4. eSRAM Intel Agilex® 7 FPGA IP v19.2.0
1.5. eSRAM Intel Agilex® 7 FPGA IP v19.1.2
1.6. eSRAM Intel Agilex® 7 FPGA IP v19.1.1
1.7. Intel Agilex® 7 Embedded Memory User Guide Archives
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.