eSRAM Intel® FPGA IP Release Notes

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ID 683604
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes 2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes x
1.1. eSRAM Intel Agilex® 7 FPGA IP v20.1.0 1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0 1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1 1.4. eSRAM Intel Agilex® 7 FPGA IP v19.2.0 1.5. eSRAM Intel Agilex® 7 FPGA IP v19.1.2 1.6. eSRAM Intel Agilex® 7 FPGA IP v19.1.1 1.7. Intel Agilex® 7 Embedded Memory User Guide Archives
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices) x
2.1. eSRAM Intel® FPGA IP v19.2.0 2.2. eSRAM Intel® FPGA IP v19.1.5 2.3. eSRAM Intel® FPGA IP v19.1.4 2.4. eSRAM Intel® FPGA IP v19.1.3 2.5. eSRAM Intel® FPGA IP v18.1 2.6. eSRAM Intel® FPGA IP v18.0 2.7. Native eSRAM IP Core v17.1 2.8. Intel® Stratix® 10 Embedded Memory User Guide Archives
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)

1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1

Table 3.  v19.2.1 2021.06.29
Intel® Quartus® Prime Version Description Impact
21.2 Fixed the hold violation by adding (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN 100"*) to the eSRAM Intel Agilex® 7 FPGA IP. The change is optional. You are required to perform an IP upgrade if your IP cannot meet the maximum performance specification due to a hold violation.
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