eSRAM Intel® FPGA IP Release Notes

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ID 683604
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes 2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes x
1.1. eSRAM Intel Agilex® 7 FPGA IP v20.1.0 1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0 1.3. eSRAM Intel Agilex® 7 FPGA IP v19.2.1 1.4. eSRAM Intel Agilex® 7 FPGA IP v19.2.0 1.5. eSRAM Intel Agilex® 7 FPGA IP v19.1.2 1.6. eSRAM Intel Agilex® 7 FPGA IP v19.1.1 1.7. Intel Agilex® 7 Embedded Memory User Guide Archives
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices) x
2.1. eSRAM Intel® FPGA IP v19.2.0 2.2. eSRAM Intel® FPGA IP v19.1.5 2.3. eSRAM Intel® FPGA IP v19.1.4 2.4. eSRAM Intel® FPGA IP v19.1.3 2.5. eSRAM Intel® FPGA IP v18.1 2.6. eSRAM Intel® FPGA IP v18.0 2.7. Native eSRAM IP Core v17.1 2.8. Intel® Stratix® 10 Embedded Memory User Guide Archives
1. eSRAM Intel Agilex® 7 FPGA IP Release Notes
2. eSRAM Intel® FPGA IP Release Notes ( Intel® Stratix® 10 Devices)

1.2. eSRAM Intel Agilex® 7 FPGA IP v20.0.0

Table 2.  v20.0.0 2021.10.04
Intel® Quartus® Prime Version Description Impact
21.3 Updated the ch{0-7}_ecc_dec_eccmode and ch{0-7}_ecc_enc_eccmode parameters to ECC_DISABLED for unused ports. IP upgrade is required to obtain the design pass compilation with Intel® Quartus® Prime Pro Edition software version 21.3.
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