Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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Date 8/05/2019
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Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes for the Intel® FPGA PAC D5005
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes for the Intel® FPGA PAC D5005 x
Acceleration Acronym List Minimum Requirements Intel® Acceleration Stack Reference Table Intel® Acceleration Stack v2.0 Features Known Issues for the Intel® Acceleration Stack v2.0 Known Issues for the Intel® Acceleration Stack v2.0 AFU Design Examples Revision History for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v2.0 Production Release Notes
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes for the Intel® FPGA PAC D5005

Intel® Acceleration Stack Reference Table

Table 2.   Intel® Acceleration Stack Best Known Configuration
Note: When the image in the user partition cannot be loaded, a flash failover occurs and the factory image is loaded instead. After a flash failover occurs, the PR ID reads as bfac4d85-1ee8-56fe-8c95-865ce1bbaa2d.
Intel® Acceleration Stack Version Platform FPGA Interface Manager (FIM) Version: Partial Reconfiguration (PR) Interface ID Open Programmable Acceleration Engine (OPAE) Version Intel® Quartus® Prime Pro Edition Board Management Controller (BMC) RTL version BMC firmware version
2.0 Intel® FPGA PAC D5005 bfac4d85-1ee8-56fe-8c95-865ce1bbaa2d 1.1.4-3 18.1.2 1.0.15 1.0.12
2.0 Pre-Beta Intel® FPGA PAC D5005 a9f2d0f3-b398-57b0-b34fd226bf364fee 1.1.4-1 18.1 1.0.6 1.0.6
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