Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005
Known Issues for the Intel® Acceleration Stack v2.0 AFU Design Examples
Known Issue | Details |
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Compilation of nlb_mode_3 AFU from source produces incorrect nlb_400.gbs output. |
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The streaming_dma_afu may contain timing violations. |
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The dma_afu may access an invalid host memory address causing a Translation Layer Packet Completion Status error (TLP CPL status error). |
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When you test the 10Gbps Ethernet AFU in loopback mode, it loses a single packet after hot plug. |
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After initial programming of the dma_afu subsequent partial reconfigurations may cause the kernel message to report errors. |
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