Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes: For the Intel FPGA Programmable Acceleration Card D5005

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Date 8/05/2019
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Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes for the Intel® FPGA PAC D5005
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes for the Intel® FPGA PAC D5005 x
Acceleration Acronym List Minimum Requirements Intel® Acceleration Stack Reference Table Intel® Acceleration Stack v2.0 Features Known Issues for the Intel® Acceleration Stack v2.0 Known Issues for the Intel® Acceleration Stack v2.0 AFU Design Examples Revision History for the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v2.0 Production Release Notes
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Release Notes for the Intel® FPGA PAC D5005

Known Issues for the Intel® Acceleration Stack v2.0

Table 4.  Known Issues for the Intel® Acceleration Stack v2.0
Known Issue Details
The system is unable to recover after a corrupted AFU is loaded onto the Intel® FPGA PAC D5005.
  • Workaround: To recover after loading a corrupted AFU onto the Intel® FPGA PAC D5005, power cycle the card.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
OPAE does not verify the images it loads on the Intel® FPGA PAC D5005.
  • Workaround: You must ensure that the images you program on the Intel® FPGA PAC D5005 come from a known and trusted source.
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
A partial reconfiguration (PR) compile using OpenCL* may produce hold time violations in the static regions.
  • Workaround: Recompile using a different seed with the command:
    aoc <kernal_name.cl> -seed=<integer>
    For example: 
    aoc hello_world.cl -seed=5
  • Status: This limitation will be fixed in a future version of the Intel® Acceleration Stack.
Invalid memory read fault may cause FIM to lock.
  • The FIM locks after the AFU sends a memory read to invalid address.
  • Workaround: Power cycle the system to reinitialize the Intel® FPGA PAC and recover from this issue. Refer to the Knowledge Base entry for more information.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
At boot, the Intel® FPGA PAC D5005 may respond to configuration read requests with non-fatal PCIe errors.
  • The Intel® FPGA PAC D5005 responds to configuration read requests to functions that do not exist by returning NonFatalErr+ error responses. You can clear and ignore these errors after boot.
  • Workaround: Clear the relevant errors at boot:
    sudo setpci -s BDF ECAP_AER+0x10.L=0xFFFFFFFF
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
When a pacd sensor trips and continues to be be tripped, pacd prints the state of the sensor at a cadence exponential to the configured polling interval.
  • Sensor output data results do not print in synchronization with the polling frequency. The frequency of the result output is equal to (polling_interval_value) multiplied by 256 seconds. For example, if the polling interval is 0, results print every second. If the interval is 1, results print every 256 seconds.
  • Workaround: Use fpgainfo command to read sensor data when required.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
The fpgainfo command returns non-critical errors that can be ignored.
  • When you run the fpgainfo command you can ignore the following results:
    • Last Power Down Cause: unavailable
    • Last Reset Cause: unavailable (can't open)
    • Socket Id : 0x00
  • Workaround: None available.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
The fpgaflash BDF value is case sensitive.
  • Workaround: When specifying BDF for card identification, you must use lowercase letters. For example, use 0000:d8:00.0 instead of 0000:D8:00.0.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
The Intel® FPGA PAC D5005 does not support optical module cables that require the ResetL pin to be driven high for link up to complete.
  • Workaround: None available.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
The /var/log/message file includes error messages on invalid rules that are not active.
  • You can ignore the following invalid rules:
    • invalid rule '/etc/udev/rules.d/40-intel-fpga.rules:1'
    • invalid ACTION operation
    • invalid rule '/etc/udev/rules.d/40-intel-fpga.rules:2'
  • Workaround: None available.
  • Status: Fix targeted for a future version of the Intel® Acceleration Stack.
After a cold boot, SPI reads from the host to the BMC using the OPAE fpgainfo bmc command may not complete.
  • Workaround: Power cycle the system.
  • Status: This limitation will be fixed in a future version of the board management controller firmware.
QSFP link and activity LEDs do not reflect Ethernet link status.
  • Workaround: None available.
  • Status: This limitation will be fixed in a future version of the board management controller firmware.
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