Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

ID 683588
Date 12/01/2017

Step 5: View Post-Fit Timing Results

After specifying clock and false path constraints, follow these steps to run full compilation and view post-fit timing analysis results. The Compiler attempts to meet your timing constraints when implementing your design, and reports paths that do not achieve the requirement.
  1. In the Compilation Dashboard, click Compile Design. The Compiler runs all stages in full compilation.
  2. Click the Timing Analyzer icon for Fitter (Finalize) in the Compilation Dashboard. The Create Timing Netlist dialog box appears automatically when the Timing Analyzer opens. Retain the default netlist settings, and then click OK.
  3. In the Tasks pane, click Update Timing Netlist. You can now generate timing analysis for the final snapshot.
  4. In the Tasks pane, double-click Report All Summaries in the Macros reports. The Timing Analyzer generates all summary reports in the Report pane.
  5. To verify that there are no violations of the clock constraints, double-click a report in the Summary (Setup) folder. The clock setup check ensures that each register-to-register transfer does not violate your .sdc clock constraints. The Slack column indicates that clk meets the requirement with some margin. The End Point TNS column reports the total negative slack (TNS) for the clock domain. Use this value to determine the number of failing paths in the clock domain.

    The clkx2 clock does not appear in the Summary (Setup) reports because of the false path constraints between clk and clkx2. The fir_filter design also contains no register-to-register paths with a destination register path clocked by clkx2.

  6. Double-click the report under the Summary (Setup) folder. The Summary (Hold) report indicates that the clk clock node meets the timing constraints by some margin.
  7. Double-click Report Top Failing Paths in the Macros reports. The report indicates "No failing paths found."