Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

ID 683588
Date 12/01/2017

Step 2: Specify Clock Constraints

The Intel® Quartus® Prime Timing Analyzer supports the industry standard Synopsys Design Constraints (.sdc) format for specifying timing constraints.

The fir_filter design example already includes a default filtref.sdc file. You can modify these constraints in the Timing Analyzer GUI, or in the .sdc file directly. Use the following steps to modify the clock constraints in the .sdc file:

  1. To launch the Timing Analyzer, click the Timing Analyzer icon for the Fitter stage you run in the Compilation Dashboard. The Create Timing Netlist dialog box opens automatically when the Timing Analyzer launches.
  2. In the Create Timing Netlist dialog box, select the compilation Snapshot, and the Delay model of the timing netlist, and then click OK.
  3. In the Timing Analyzer, click File > Open, and then select the filtref.sdc file in the project directory. The file opens in the Intel® Quartus® Prime Text Editor.
  4. In the .sdc file, locate the following two create_clock constraints:
    # Create Clock
    create_clock -name {clk} -period 4.000 -waveform { 0.000 2.000 } /
         [get_ports {clk}]
    create_clock -name {clkx2} -period 4.000 -waveform { 0.000 2.000 } /
         [get_ports {clkx2}]
  5. Replace the existing clock constraints with the following clock constraints. The replacement defines a 50 MHz (50/50 duty cycle) clock for clk, and a 100 MHz (60/40 duty cycle) clock for clkx2.
    # Create Clock
    create_clock -name clk -period 20 [get_ports {clk}]
    create_clock -name clkx2 -period 10.000 -waveform {0 6} /
         [get_ports {clkx2}]
    Note: For help entering .sdc constraints, right-click anywhere in the text file, point to Insert Constraint, and then select the constraint to insert at the cursor location.
  6. To save the .sdc file changes, click File > Save.
  7. To load the updated .sdc constraints, double-click Read SDC File in the Tasks pane.
  8. To update the timing netlist, double-click Update Timing Netlist.