Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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ID 683588
Date 12/01/2017
Public

Step 4: Declare False Paths

Follow these steps to declare false paths for the clock transfers between the clk and clkx2 clock signals:
  1. In the Timing Analyzer, click File > Open, and open filtref.sdc.
  2. In the .sdc file, locate the following get_false_path constraint: 
    #**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {clk clkx2}] -through /
     [get_pins -compatibility_mode *] -to [get_clocks {clk clkx2}]
  3. To declare false paths for all clock transfers between the clk and clkx2 clock signals, replace the existing false path constraint with the following: 
    #**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks clk] /
     -to [get_clocks clkx2]
  4. Save and close the .sdc file.
  5. To load the new .sdc constraints, double-click Read SDC File in the Tasks pane.
  6. To update the timing netlist, double-click Update Timing Netlist.
  7. To confirm the false path assignment in the reports, double-click Setup Transfers in the Diagnostic reports. The RR Paths column indicates that the clock domain is now a "false path," reflecting your constraint.
Level Two Title