This tutorial uses a simple fir_filter design to demonstrate the Intel® Quartus® Prime Timing Analyzer.
The Intel® Quartus® Prime software installation includes the sample fir_filter project in the quartus/qdesigns/fir_filter/ directory. The following steps describe opening the example project and running initial compilation to elaborate the design hierarchy, synthesize logic, and generate a node netlist for application of constraints.
- Launch the Intel® Quartus® Prime Pro Edition software.
- To open the example design project, click , and open the quartus/qdesigns/fir_filter/fir_filter.qpf project file.
- To view the top-level design schematic, click Open on the Tasks pane, select the filtref.bdf file, and click Open. The filtref.bdf schematic appears in the Block Editor.
- Perform one of the following from the Compilation Dashboard. (To display the Dashboard if closed, click ).
- To run the Fitter, click Fitter (or any Fitter stage) on the Compilation Dashboard.
- To run a full compilation, click Compile Design on the Compilation Dashboard.