Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

ID 683577
Date 3/27/2023

3.1.1. MLAB

Each MLAB supports a maximum of 640 bits of simple dual-port SRAM. You can configure each ALM in an MLAB as a 32 (depth) x 2 (width) memory block, resulting in a configuration of 32 (depth) x 20 (width) simple dual-port SRAM block.

Figure 2.  Intel Agilex® 7 LAB and MLAB Structure