Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

ID 683577
Date 3/27/2023

3.1.4. LAB Control Signals

There are two clock sources in each LAB control block, which generate two LAB clocks (LABCLK[1:0]) and two delayed LAB clocks (LABCLK_Phi1[1:0]) to drive the ALM registers and Hyper-Registers in the LAB. The LAB supports two unique clock enable signals, as well as additional clear signals, for the ALM registers.

The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. A low skew clock network distributes global signals to the row clocks [5..0]. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for routing efficiency. The Intel® Quartus® Prime Compiler automatically routes critical design paths on faster interconnects to improve design performance and optimizes the device resources.