Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683577
Date 3/27/2023
Public

4. Document Revision History for the Intel Agilex® 7 Logic Array Blocks and Adaptive Logic Modules User Guide

Document Version Changes
2023.03.27 Updated product family name to "Intel Agilex® 7".
2022.05.24 Updated Figure: Intel Agilex® 7 ALM High-Level Block Diagram.
2019.11.14 Updated the description in the LAB Control Signals section.
2019.10.01
  • Updated the details for the synchronous and asynchronous clear signals in the Clear Logic Control section.
  • Updated Figure: Intel Agilex® 7 LAB Structure and Interconnects Overview.
  • Updated Figure: Intel Agilex® 7 LAB Local and Direct Link Interconnects.
  • Updated Figure: Intel Agilex® 7 ALM Connection Details.
  • Updated Figure: Intel Agilex® 7 LAB-Wide Control Signals.
  • Updated Figure: Intel Agilex® 7 ALM High-Level Block Diagram.
  • Removed the Time Borrowing and Latch Modes section.
2019.04.02 Initial release.
Level Two Title