Visible to Intel only — GUID: prr1651627043921
Ixiasoft
Visible to Intel only — GUID: prr1651627043921
Ixiasoft
2.3.1.4. Xcelium* Simulator
- AGIx027R29AxxxxR3
- AGIx027R29AxxxxR2
- AGIx027R29BxxxxR3
- AGIx023R18AxxxxR0
- AGIx041R29DxxxxR0
- AGIx041R29DxxxxR1
- AGMx039R47AxxR0
- Export the following environment variables:
- export CADENCE_ENABLE_AVSREQ_6614_PHASE_1=1
- export CADENCE_ENABLE_AVSREQ_12055_PHASE_1=1
- Change to the simulation working directory: cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/xcelium
- Execute the following command:
sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="-sv\ +define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" DEFAUL_ELAB_OPTIONS="-access\ +r+w" USER_DEFINED_SIM_OPTIONS="-input\ @run" TOP_LEVEL_NAME="pcie_ed_sim_tb.pcie_ed_sim_tb" | tee simulation.log
Note: The command above is a single-line command.
- cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/xcelium/
- sh run_xcelium.sh
A successful simulation includes the following message: "Simulation stopped due to successful completion!"
