R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/07/2025
Public
Document Table of Contents

2.3.1.2. VCS* Simulator

Perform the following steps to execute the simulation via a command line:
  1. Change to the simulation working directory: cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/synopsys/vcs.
  2. Execute the following command:

    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_SIM_OPTIONS="" DEVICES_SIM_LIB_DIR=$QUARTUS_ROOTDIR/../devices/sim_lib2 QUARTUS_SIM_LIB_DIR=$QUARTUS_ROOTDIR/eda/sim_lib2 TOP_LEVEL_NAME="pcie_ed_sim_tb" | tee simulation.log

    Note: The command above is a single-line command.
    Note: Only use the +RTILE_PIPE_MODE option when the Enable PIPE Mode Simulation for Example Design parameter is checked.
If R-Tile is configured with Enable PIPE Mode Simulation for Example Design, use the following steps instead:
  1. cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/synopsys/vcs/
  2. sh run_vcs.sh

A successful simulation includes the following message: "Simulation stopped due to successful completion!"

Perform the following steps to execute the simulation in interactive mode. Note that in case you have already generated a simv executable in non-interactive mode, you need to delete the simv file and simv.diadir directory.
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -kdb -debug_access+all
  2. Execute the following command:

    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_SIM_OPTIONS="" DEVICES_SIM_LIB_DIR=$QUARTUS_ROOTDIR/../devices/sim_lib2 QUARTUS_SIM_LIB_DIR=$QUARTUS_ROOTDIR/eda/sim_lib2 TOP_LEVEL_NAME="pcie_ed_sim_tb" SKIP_SIM=1 | tee simulation.log

    Note: If R-Tile is configured with Enable PIPE Mode Simulation for Example Design active, use the following command:

    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RTILE_PIPE_MODE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_SIM_OPTIONS="" DEVICES_SIM_LIB_DIR=$QUARTUS_ROOTDIR/../devices/sim_lib2 QUARTUS_SIM_LIB_DIR=$QUARTUS_ROOTDIR/eda/sim_lib2 TOP_LEVEL_NAME="pcie_ed_sim_tb" SKIP_SIM=1 | tee simulation.log

  3. Start the simulation in interactive mode: simv -gui &