R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2.3.1.2. VCS* Simulator
- Change to the simulation working directory: cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/synopsys/vcs.
- Execute the following command:
sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_SIM_OPTIONS="" DEVICES_SIM_LIB_DIR=$QUARTUS_ROOTDIR/../devices/sim_lib2 QUARTUS_SIM_LIB_DIR=$QUARTUS_ROOTDIR/eda/sim_lib2 TOP_LEVEL_NAME="pcie_ed_sim_tb" | tee simulation.log
Note: The command above is a single-line command.Note: Only use the +RTILE_PIPE_MODE option when the Enable PIPE Mode Simulation for Example Design parameter is checked.
- cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/synopsys/vcs/
- sh run_vcs.sh
A successful simulation includes the following message: "Simulation stopped due to successful completion!"
- Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -kdb -debug_access+all
- Execute the following command:
sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_SIM_OPTIONS="" DEVICES_SIM_LIB_DIR=$QUARTUS_ROOTDIR/../devices/sim_lib2 QUARTUS_SIM_LIB_DIR=$QUARTUS_ROOTDIR/eda/sim_lib2 TOP_LEVEL_NAME="pcie_ed_sim_tb" SKIP_SIM=1 | tee simulation.log
Note: If R-Tile is configured with Enable PIPE Mode Simulation for Example Design active, use the following command:sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+RTILE_OVERCLK_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+RTILE_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+RTILE_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+RTILE_FASTSIM\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+RTILE_PIPE_MODE\ +define+RNR_FASTSIM_AIB_BYPASS" USER_DEFINED_SIM_OPTIONS="" DEVICES_SIM_LIB_DIR=$QUARTUS_ROOTDIR/../devices/sim_lib2 QUARTUS_SIM_LIB_DIR=$QUARTUS_ROOTDIR/eda/sim_lib2 TOP_LEVEL_NAME="pcie_ed_sim_tb" SKIP_SIM=1 | tee simulation.log
- Start the simulation in interactive mode: simv -gui &