R-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683544
Date 10/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Functional Descriptions of the Design Examples 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
1. Functional Descriptions of the Design Examples x
1.1. Glossary of Terms 1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
1.2. Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express x
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.2.3. Functional Description for the Performance Design Example 1.2.4. Functional Description for the Performance Design Example for TL Bypass Mode 1.2.5. Hardware and Software Requirements
1.2.1. Functional Description for the Programmed Input/Output (PIO) Design Example x
1.2.1.1. Credit Initialization Sequence
1.2.1.1. Credit Initialization Sequence x
1.2.1.1.1. Credit Value Initialization and Return 1.2.1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example
2.2. Generating the Design Example x
2.2.1. Generating the Design Example with R-Tile Configured in PIPE Mode 2.2.2. Generating the Performance Design Example for TL Bypass Mode
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Siemens EDA QuestaSIM* Simulator 2.3.1.2. VCS* Simulator 2.3.1.3. VCS* MX Simulator 2.3.1.4. Xcelium* Simulator 2.3.1.5. Riviera* Simulator
2.3.2. Testbench x
2.3.2.1. Testbench Modules 2.3.2.2. Test Driver Module 2.3.2.3. PIO Design Example Testbench 2.3.2.4. SR-IOV Design Example Testbench
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
2.7. Running the Design Example x
2.7.1. Running the PIO Design Example 2.7.2. Running the SR-IOV Design Example 2.7.3. Running the Performance Design Example (Endpoint) 2.7.4. Running the Performance Design Example for TL Bypass Mode
1. Functional Descriptions of the Design Examples
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

4. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.10.28 25.1 11.6.0 Added a Note to Siemens EDA QuestaSIM* Simulator.
2025.04.07 25.1 11.6.0
  • Added the Riviera simulator to the list of supported simulators in Overview of the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express.
  • Added the Riviera simulator to the list of supported simulators in Functional Description for the Programmed Input/Output (PIO) Design Example.
  • Added the Riviera simulator to the list of supported simulators in Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example.
  • Added the Riviera Simulator section.
2025.01.27 24.3.1 11.5.0
  • Updated the description in Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example.
  • Updated the total number of Virtual Functions of PF0 and PF1 in Generating the Design Example.
  • Added a Note to Generating the Design Example with R-Tile Configured in PIPE Mode.
  • Updated the simulation instructions for all the simulators under Steps to Run Simulations.
2024.11.05 24.3 11.4.0
  • Updated the description in Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example.
  • Updated the number of Virtual Functions for Physical Function 0 (PF0) and Physical Function 1 (PF1) in Generating the Design Example.
2024.10.07 24.3 11.4.0
  • Updated the simulation commands in VCS* Simulator.
  • Updated the simulation commands in VCS* MX Simulator.
  • Updated the simulation commands in Xcelium Simulator Xcelium* Simulator.
2024.07.08 24.2 11.3.0
  • Added the Reset Release block to all block diagrams in Chapter 1.
  • Added notes to the Functional Description sections for the PIO and SR-IOV design examples stating that these design examples support payload sizes of up to 388 bytes only.
  • Updated some procedures in the BFM Procedures and Functions section to change the arguments of imm_regb_ad, imm_regb_adr, and length to regb_ad, regb_adr, and leng, respectively.
  • Added the new section Generating the Design Example with R-Tile Configured in PIPE Mode. Added a Note mentioning that PIPE mode simulation is supported for the VCS and VCSMX simulators only in the current release.
  • Updated the VCS Simulator section to add the command to run VCS simulations when R-Tile is configured in PIPE Direct mode.
2024.04.12 24.1 11.2.0
  • Added the Performance design example for TL Bypass mode to Table 1 in About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express.
  • Added section Functional Description for the Performance Design Example for TL Bypass Mode to Chapter 1 About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express.
  • Added section Generating the TL Bypass Performance Design Example to section Generating the Design Example.
2023.12.04 23.4 11.1.0
  • Updated the description and block diagrams in the Functional Description for the Programmed Input/Output (PIO) Design Example section.
  • Updated the description in the Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example section.
2023.10.19 23.3 11.0.0 Updated the screenshots showing the results of running the Maximum Performance Test in the Running the Performance Design Example section.
2023.10.02 23.3 11.0.0 Added steps to run the Performance design example 2x8 to the Running the Performance Design Example section.
2023.06.26 23.2 10.0.0

Changed the Quartus® Prime version number and IP version number.
2023.04.03 23.1 9.0.0
  • Updated product family name to " Agilex™ 7"
  • Added a new section Functional Description for the Performance Design Example
  • Added a new section Running the Performance Design Example
2022.12.19 22.4 8.0.0 Updated the ACDS version number and the IP version number.
2022.09.26 22.3 7.0.0
  • Added the section Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example.
  • Added steps to generate the SR-IOV design example to the section Generating the Design Example.
  • Added the section SR-IOV Design Example Testbench.
  • Added the section Running the SR-IOV Design Example.
2022.06.20 22.2 6.0.0 Added a section on how to simulate the design example using the Xcelium* simulator.
2022.03.28 22.1 5.0.0
  • Added a summary table of all the configurations supported by this design example to the Design Example Description section.
  • Added the Hardware and Software Requirements section.
  • Updated the Simulating the Design Example section to include clearer instructions on how to simulate the design example using various simulators.
2021.12.13 21.4 4.0.0 Added support for the Gen4 x16, Gen3 x16, Gen4 2x8 and Gen3 2x8 design examples.
2021.10.04 21.3 3.0.0 Added instructions on how to simulate the design example using the VCS* MX simulator to the section Simulating the Design Example.
2021.07.12 21.2 2.0.0 Initial release.
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