R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/10/2023

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2.3. Simulating the Design Example

The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the R-tile Avalon® Streaming Intel FPGA IP for PCIe (DUT) as shown in the following figure.

Figure 17. PIO Design Example Simulation Testbench
Figure 18. SR-IOV Design Example Simulation Testbench

For a more detailed description of the testbench and the modules inside it, refer to Testbench. Also, for more details on the Root Port BFM specifically, refer to the Root Port BFM section.

The following flow diagram shows the steps to simulate the design example:

Figure 19. Procedure
Note: R-tile does not support parallel PIPE simulations.

The following figure shows the link status information for a Gen5 x16 Endpoint simulation:

Figure 20. Link Status for a Gen5 x16 Endpoint Simulation

After a successful simulation, the simulation.log file contains a "successful completion" message.

This testbench simulates up to a Gen5 x16 variant.