R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/10/2023

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Document Table of Contents Credit Value Initialization and Return

The following table shows an example of a posted 1024-bit write sequence consuming one posted header credit and eight posted data credits.

Table 3.  Example of a 1024-bit Posted Write Sequence
Header               H0
Data D7 D6 D5 D4 D3 D2 D1 D0

A non-posted read sequence consumes one non-posted header credit only as shown in the table below.

Table 4.  Example of a Non-Posted Read Sequence
Header H0