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1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express Design Example User Guide
2.4.5.1. ebfm_barwr Procedure
2.4.5.2. ebfm_barwr_imm Procedure
2.4.5.3. ebfm_barrd_wait Procedure
2.4.5.4. ebfm_barrd_nowt Procedure
2.4.5.5. ebfm_cfgwr_imm_wait Procedure
2.4.5.6. ebfm_cfgwr_imm_nowt Procedure
2.4.5.7. ebfm_cfgrd_wait Procedure
2.4.5.8. ebfm_cfgrd_nowt Procedure
2.4.5.9. BFM Configuration Procedures
2.4.5.10. BFM Shared Memory Access Procedures
2.4.5.11. BFM Log and Message Procedures
2.4.5.12. Verilog HDL Formatting Functions
2.4.5.11.1. ebfm_display Verilog HDL Function
2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function
2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task
2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
2.4.5.11.5. ebfm_log_open Verilog HDL Function
2.4.5.11.6. ebfm_log_close Verilog HDL Function
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2.7.3. Running the Performance Design Example
- Navigate to ./software/user/example under the design example directory.
- Compile the design example application:
$ make
- Run the test:
$ sudo ./intel_fpga_pcie_link_test
You can run the Intel FPGA IP PCIe link test in manual or automatic mode. Choose from:- In automatic mode, the application automatically selects the device. The test selects the Intel PCIe device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
- In manual mode, the test queries you for the bus, device, and function numbers and BAR.
For the Intel Agilex® 7 Development Kit, you can determine the BDF by typing the following command:
$ lspci -d 1172:
- Here is a sample transcript for the selection between automatic and manual modes:
# ./intel_fpga_pcie_link_test ********************************************************* Intel FPGA PCIe Link Test Version 2.0 0: Automatically select a device 1: Manually select a device *********************************************************
- The Performance design example for the Intel FPGA IP R-Tile Avalon Streaming Hard IP for PCI Express IP core only supports menu option 9. Enter 9 and press Enter to proceed.
Opened a handle to BAR 0 of a device with BDF 0x3800 ********************************************************* 0: Link test - 100 writes and reads 1: Write memory space 2: Read memory space 3: Write configuration space 4: Read configuration space 5: Change BAR for PIO 6: Change device 7: Enable SRIOV 8: Do a link test for every enabled virtual function belonging to the current device 9: Perform DMA for Throughput 10: Quit program ********************************************************* > 9
- Select option 0: Execute Max Traffic Test
********************************************************* END POINT (EP) ORIGINATED TRAFFIC 0: Execute Max Traffic Test 1: Quit ********************************************************* > 0 ********************************************************* MAX END POINT (EP) TRAFFIC ********************************************************* EXECUTING WRITE TRAFFIC... 100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||] PERF WRITE GB/s: 59.94 EXECUTING READ TRAFFIC... 100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||] PERF READ GB/s: 59.1 EXECUTING WRITE & READ TRAFFIC... 100% [||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||] PERF WRITE GB/s: 55.51 PERF READ GB/s: 56.87 *********************************************************