R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/10/2023
Public

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2.3.1.1. Siemens EDA QuestaSim* Simulator

Perform the following steps:
  1. Change to the simulation working directory: cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/mentor.
  2. Invoke vsim, which brings up a console window where you can run the next commands: Type vsim
    1. set TOP_LEVEL_NAME "pcie_ed_tb.pcie_ed_tb"
    2. do msim_setup.tcl
    3. ld_debug
    4. run -all

A successful simulation includes the following message: "Simulation stopped due to successful completion!"

Note: When running simulations under Windows* OS, if your project path is too long, you may encounter access errors to the design files. To avoid this, shorten your project path as much as possible. The longest path for any design file should be less than 189 characters.