R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/10/2023

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Document Table of Contents

1.1.1. Credit Initialization Sequence

In R-tile, the back-pressure mechanism by the PIO component is done through the credit system. Therefore, the credit value must be declared during the credit initialization stage. An initial TX credit value is captured by the DUT and deducted for any TLP sent to the PIO. When the credit value reaches zero, the DUT stops sending any more TLP until the PIO returns the credit.

For the R-tile design example, the RX_CRDT_INIT block interfaces with the credit signals from the DUT as shown in the figure below. The block focuses on initializing and returning the RX credit. In the TX direction, the block only asserts crdt_init_ack to complete the initialization stage. The PIO component captures the TX credit during the initialization stage initiated by the DUT.

Figure 6. Credit System of the Design Example

The waveforms below show the initialization sequence for RX credit from PIO to DUT. During the initialization phase, the PIO asserts the *crdt_init signal. In response, the DUT asserts the *crdt_init_ack signal. After receiving the ack signal, the PIO asserts *crdt_update and the internal crdt_cnt of the DUT captures the *crdt_update_cnt value.

Figure 7. Waveforms of Credit Transactions During the Initialization Stage