AN 869: Partially Reconfiguring a Design: on Intel® Cyclone® 10 GX FPGA Development Board

ID 683503
Date 7/15/2019

Step 4: Adding the Partial Reconfiguration Controller IP

The Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 GX FPGA IP enables reconfiguration of the PR partition via .
Follow these steps to add the IP core to your Intel® Quartus® Prime project:
  1. Type Partial Reconfiguration in the IP Catalog (Tools > IP Catalog).
  2. Double-click Intel® Arria® 10/Cyclone 10 GX FPGA IP.
  3. In the Create IP Variant dialog box, type pr_ip as the File Name, and then click Create. The parameter editor appears
  4. Turn on Use as partial reconfiguration internal host, Enable JTAG debug mode, and Enable freeze interface. Turn off Enable Avalon-MM slave interface.
    Figure 7. Partial Reconfiguration Controller IP Core Parameters
  5. Click File > Save, and exit the parameter editor without generating the system. The parameter editor generates the pr_ip.ip IP variation file and adds the file to the blinking_led project.
    1. If you are copying the pr_ip.ip file from the pr folder, manually edit the blinking_led.qsf file to include the following line:
      set_global_assignment -name IP_FILE pr_ip.ip
    2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration Controller IP core.
      Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or .sdc files that you use to create these clocks in the .qsf file for your Intel® Quartus® Prime project revision. For more information, refer to the Partial Reconfiguration IP Solutions User Guide.

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