AN 869: Partially Reconfiguring a Design: on Intel® Cyclone® 10 GX FPGA Development Board

ID 683503
Date 7/15/2019
Public

Updating the Top-Level Design

To update the top.sv file with the PR_IP instance:
  1. To add the pr_ip instance to the top-level design, uncomment the following code block in top.sv file:
    pr_ip u_pr_ip
        (
            .clk           (clock),
            .nreset        (1'b1),
            .freeze        (freeze),
            .pr_start      (1'b0),            // ignored for JTAG
            .status        (pr_ip_status),
            .data          (16'b0),
            .data_valid    (1'b0),
            .data_ready    ()
        );
  2. Save the file.
Figure 8. Partial Reconfiguration IP Core Integration

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