AN 869: Partially Reconfiguring a Design: on Intel® Cyclone® 10 GX FPGA Development Board

ID 683503
Date 7/15/2019
Public

Reference Design Files

The partial reconfiguration tutorial is available in the following location:

https://github.com/intel/fpga-partial-reconfig

To download the tutorial:
  1. Click Clone or download.
  2. Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
  3. Navigate to the tutorials/c10_pcie_devkit_blinking_led sub-folder to access the reference design.

The flat folder consists of the following files:

Table 1.  Reference Design Files
File Name Description
top.sv

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.

top_counter.sv Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc

Defines the timing constraints for the project.

blinking_led.sv This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].
blinking_led.qpf

Intel® Quartus® Prime project file containing the list of all the revisions in the project.

blinking_led.qsf

Intel® Quartus® Prime settings file containing the assignments and settings for the project.

Note:

The pr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.

Figure 2. Reference Design Files

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