Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 12/04/2023
Public
Document Table of Contents

2.1.3. Acronyms

This document uses the following acronyms throughout:
Acronym Meaning
ALR Additional Logic Resources
DSE Design Space Explorer
DSP Digital Signal Processing
EDA Electronic Design Automation
EDS Embedded Design Suite
EPE Early Power Estimator
FIFO First In, First Out
FPGA Field Programmable Gate Arrays
GUI Graphical User Interface
HDL Hardware Description Language
HTML HyperText Markup Language
HPS Hard Processor System
IEEE Institute of Electrical and Electronics Engineers
IP Intellectual Property
JTAG Joint Test Action Group
LAB Logic Array Block
LAI Logic Analyzer Interface
MTBF Mean Time Between Failures
PCB Printed Circuit Board
PLD Programmable Logic Devices
PLLs Phase-Locked Loops
PTC Power and Thermal Calculator
PVT Process, Voltage, and Temperature
QSF Quartus Settings File
RAM Random-Access Memory
RTL Register-Transfer Level or Register-Transfer Logic
SDC Synopsys* Design Constraints
Tcl Tool Command Language
UART Universal Asynchronous Receiver-Transmitter
VCS Verilog Compiler and Simulator
VHDL Very High Speed Integrated Circuit Hardware Description Language
VPN Virtual Private Network
VREF Voltage Reference