1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
2.2. The Project Directory
The project directory ( <result>.prj) that the Intel® HLS Compiler Pro Edition outputs has four subdirectories.
|Contains a folder for each component, and all HDL and IP files that are needed to use that component in a design.
|Contains all the files for the verification testbench.
|Contains the High-Level Design Reports. The High-Level Design Reports are a set of reports and viewers that you open in a web browser. Use the reports to analyze the synthesized hardware implementation of your components and tasks.
|Contains an Intel® Quartus® Prime project that instantiates the components. You can compile this Intel® Quartus® Prime project to generate more detailed timing and area reports.
Do not use the contents of this subdirectory to integrate your component in a design. Use the contents of the components directory.