Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 12/13/2021
Public

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A.2.1.2.1. Reviewing Component Interfaces

The Function View of the System Viewer shows a visual representation of the interfaces in your component.

Some parameters in your component can be marked as being stable. A parameter can be marked as stable if its argument does not change while your component executes, but the argument might change between component executions. In the Function View, a stable argument does not have any edge connection.

Default (Conduit) Interfaces

Conduit interfaces are implemented for any function parameter whose arguments are passed by value. The Function View of the System Viewer report connects the conduit interface to the corresponding stream read (RD) node. The read is synchronized with the start/busy signals on the component invocation interface.
#include "HLS/hls.h"

struct coordinate_t {
	int x;
	int y;
};

component int default_comp(int b, coordinate_t p) {
	return b + p.x;
}


For each default interface argument node, you can view details about the node in the Details pane when you hover over the node:

Avalon® MM Host Interfaces

Pointer arguments, pass-by-reference arguments, ihc::mm_host<> argument, and global variables all correspond to addresses to memory outside of your component. They result in at least one Avalon® MM Host interface in your component.

Each ihc::mm_host<> argument of a component results in an input conduit for the base address, which is connected to a Read node in the system viewer. In addition to this input conduit, a unique Avalon MM Host interface is created for each address space. This interface is connected to one or more Load or Store nodes in the system viewer.
#include "HLS/hls.h"

component int
host_comp(int *pointer_d,
            ihc::mm_host<int, ihc::aspace<3>, ihc::awidth<4>, ihc::dwidth<32>,
                           ihc::latency<1>, ihc::align<4>> &host_i,
            int &result) {
  result = pointer_d[0] + host_i[0];
  return result;
}

The Function View of the System Viewer shows the following details for these interface arguments:
Stable
Describes whether the interface argument is stable. That is, whether the hls_stable_argument attribute was applied.
Data width
The width of the memory-mapped data bus in bits.
Address width
The width of the memory-mapped address bus in bits.
Latency
The guaranteed latency from when the read command exits the component to when the external memory returns valid read data. The latency is measured in clock cycles.
Maximum burst
The maximum number of data transfers that can associate with a read or write transaction. For fixed latency interfaces, this value is set to 1.
Alignment
The byte alignment of the base pointer address. The Intel® HLS Compiler uses this information to determine the amount of coalescing that is possible for loads and stores to this pointer.

The Function View of the System Viewer shows the following details for Avalon® MM Host interfaces:
Memory address space number
The memory address space number for Avalon® MM Host interface.
Number of banks
The number of memory banks contained in the memory.
Argument Name:
The names of arguments that access the Avalon® MM Host interface.

Avalon® MM Agent Register Interfaces

When you label a function parameter as an Avalon® MM agent register (hls_avalon_agent_register_argument), then the interface argument is implemented in the control and status register (CSR) agent interface. The Function View of the System Viewer puts the agent register arguments inside a CSR container.
#include "HLS/hls.h"

component int agentreg_comp(
  int hls_avalon_agent_register_argument agent_scalar_f,
  int* hls_avalon_agent_register_argument agent_pointer_g
  ) {
  return agent_scalar_f + *agent_pointer_g;
}

The resulting memory map is described in the automatically generated header file <component_name>_csr.h. This header file is available in the menu in the source code pane. Clicking on the CSR container node in the Function View of the System Viewer also opens up the header file:

If you use the hls_avalon_agent_component macro, then the call and return signals from the component invocation interface are implemented in the control-and-status register (CSR) interface:
#include "HLS/hls.h"

hls_avalon_agent_component
component int agentreg_comp(
  int hls_avalon_agent_register_argument agent_scalar_f,
  int* hls_avalon_agent_register_argument agent_pointer_g
  ) {
  return agent_scalar_f + *agent_pointer_g;
}

Avalon® MM Agent Memory Interfaces

When you declare a pointer argument as a agent memory, the Function View of the System Viewer shows the agent memory interface with a <agent memory name> LD/ST node that is connected to the Local Memory node in the component.
#include "HLS/hls.h"

hls_avalon_agent_component
component int agentmem_comp(
  hls_avalon_agent_memory_argument(4096) int* agent_mem_h,
  int hls_stable_argument index,
  int hls_avalon_agent_register_argument agent_scalar_f
  ) {
  return agent_mem_h[index] * agent_scalar_f;
}

Avalon® Streaming Interfaces

A streaming interface is shown in the Function View of the System Viewer by a <stream name> node connected to the corresponding RD node (for stream_in<>) or WR node (for stream_out<>).
#include "HLS/hls.h"

component int stream_comp(
  ihc::stream_in<int> &stream_in_c,
  ihc::stream_out<int> &stream_out_e,
  int scalar_b
  ) {

  stream_out_e.write(scalar_b + 1);
  return  stream_in_c.read() + scalar_b * 2;
} 

The Function View of the System Viewer shows the following details for streaming interface arguments:
Width
The width of the data signal in bits.
Depth
The depth of the stream in words

The word size of the stream is the size of the stream datatype.

Bits per symbol
Describes how the data is broken into symbols on the data bus.
Uses Packets
Indicates whether the interface exposes the startofpacket and endofpacket sideband signals on the stream interfaces. The signals can be access by the packet-based reads and writes.
Uses Valid
(stream_in) Indicates whether a valid signal is present on the stream interface. When Yes, the upstream source must provide valid data on every cycle that ready is asserted.
Uses Ready
(stream_out) Indicates whether a ready signal is present on the stream interface. When Yes, the downstream sink must be able to accept data on every cycle that valid is asserted.

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