Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 12/13/2021

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Document Table of Contents

A. Reviewing Loops and Blocks in Your Component or Task

The Function Views of the System Viewer in the High Level Design Report (report.html) shows an abstracted netlist of your component design. In the Function Views, you can visualize loops in your component and your component interactions with its internal RAM block and external interfaces.

Consider the following code excerpt from the transpose_and_fold component (part of the tutorial files provided in <quartus_installdir>/hls/examples/tutorials/best_practices/loop_memory_dependency):
#include "HLS/hls.h"
#include <stdio.h>
#include <stdlib.h>

#define SIZE 4

typedef ihc::stream_in<int> my_operand;
typedef ihc::stream_out<int> my_result;

component void transpose_and_fold(my_operand &data_in, my_result &res)
  int i;
  int j;
  int in_buf[SIZE][SIZE] hls_memory;
  int tmp_buf[SIZE][SIZE] hls_memory;
  for (i = 0; i < SIZE * SIZE; i++) {
    in_buf[i / SIZE][i % SIZE] =;
    tmp_buf[i / SIZE][i % SIZE] = 0;

  #ifdef USE_IVDEP
  #pragma ivdep safelen(SIZE)
  for (j = 0; j < SIZE * SIZE * SIZE; j++) {
  #pragma unroll
    for (i = 0; i < SIZE; i++) {
      tmp_buf[j % SIZE][i] += in_buf[i][j % SIZE];
  for (i = 0; i < SIZE * SIZE; i++) {
    res.write(tmp_buf[i / SIZE][i % SIZE]);

The Details pain in the report shows that transpose_and_fold.B4 is a pipelined loop with an II value of 6. The loop pipeline with this II value might affect the throughput of your design.

Figure 4. Function View of the transpose_and_fold Component

You can investigate further by checking the Loop Analysis report.

The Bottlenecks pane in the Loop Analysis Report shows that the II value is caused by a memory dependency on loads to the tmp_buf variable:
Figure 5. Loop Analysis Report Bottleneck and Details Panes for transpose_and_fold.B4

To see more information about the LSU in the System Viewer report, click on a node to display information about the LSU in the Details pane. In the figure below, the Details pane shows information like the latency and that the LSU is stall-free.

For stallable nodes, latency values provided are estimates.

Figure 6. Information in Details Pane for an LSU
When viewing a function, the Function View pane shows connections between nodes:
  • Control

    Control connections are connections between blocks and loops.

  • Memory

    Memory connections are connections between local memories, agent memories, or Avalon® MM Host interfaces.

  • Streams

    Stream connections are connections to and from read or write streams

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